--
-- VHDL Architecture vga_module_lib.test.arch
--
-- Created:
--          by - erial674.student (southfork-15.edu.isy.liu.se)
--          at - 10:06:35 10/04/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY color_controller IS
   PORT( 
      vga_b    : OUT    std_logic_vector ( 9 DOWNTO 0 );
      vga_g    : OUT    std_logic_vector ( 9 DOWNTO 0 );
      vga_r    : OUT    std_logic_vector ( 9 DOWNTO 0 );
      vga_sync : OUT    std_logic;
      fpga_clk : IN     std_logic;
      vga_clk  : IN     std_logic;
      pcnt     : IN     integer RANGE 0 TO 794;
      lcnt     : IN     integer RANGE 0 TO 525
   );

-- Declarations

END color_controller ;

--
ARCHITECTURE arch OF color_controller IS
  signal amplitude1 : integer range 0 to 23;
  signal amplitude2 : integer range 0 to 23;
  signal amplitude3 : integer range 0 to 23;
  signal amplitude4 : integer range 0 to 23;
  signal amplitude5 : integer range 0 to 23;
  signal amplitude6 : integer range 0 to 23;
  signal amplitude1_bar : integer range 0 to 9;
  signal amplitude2_bar : integer range 0 to 9;
  signal amplitude3_bar : integer range 0 to 9;
  signal amplitude4_bar : integer range 0 to 9;
  signal amplitude5_bar: integer range 0 to 9;
  signal amplitude6_bar : integer range 0 to 9;

  signal amplitude : std_logic_vector (9 downto 0);  
  
  signal volume : integer range 0 to 9; 
  signal balance : integer range 0 to 10;
  
  signal l_cnt_to_amplitude : integer range 0 to 23;
  
  signal ypos_in_bands : std_logic;  
  signal in_band1 : std_logic;
  signal in_band2 : std_logic;
  signal in_band3 : std_logic;
  signal in_band4 : std_logic;
  signal in_band5 : std_logic;
  signal in_band6 : std_logic;
  signal in_band1_bar : std_logic;
  signal in_band2_bar : std_logic;
  signal in_band3_bar : std_logic;
  signal in_band4_bar : std_logic;
  signal in_band5_bar : std_logic;
  signal in_band6_bar : std_logic;
  
  signal ypos_in_volume_and_blance : std_logic;
  signal in_volume : std_logic;
  signal in_balance : std_logic;
  signal in_volume_bar : std_logic;
  signal in_balance_bar : std_logic;
  
BEGIN
  
  vga_sync <= '0';
  
-- TODO: Load this values from Equalizer when v_sync
  amplitude1 <= 15;
  amplitude2 <= 10;
  amplitude3 <= 13;      
  amplitude4 <= 1;
  amplitude5 <= 0;
  amplitude6 <= 23;
  
  amplitude1_bar <= 5;
  amplitude2_bar <= 9;
  amplitude3_bar <= 3;      
  amplitude4_bar <= 7;
  amplitude5_bar <= 0;
  amplitude6_bar <= 4;
  
  volume <= 6;
  balance <= 5;
  
  l_cnt_to_amplitude <= (384+9-lcnt)/16;
  
  ypos_in_bands <= '1' when 9 < lcnt and lcnt < 393 else '0';
  in_band1 <= '1' when 38  < pcnt and pcnt < 98  and ypos_in_bands = '1' else '0';
  in_band2 <= '1' when 138 < pcnt and pcnt < 198 and ypos_in_bands = '1' else '0';
  in_band3 <= '1' when 238 < pcnt and pcnt < 298 and ypos_in_bands = '1' else '0';
  in_band4 <= '1' when 338 < pcnt and pcnt < 398 and ypos_in_bands = '1' else '0';
  in_band5 <= '1' when 438 < pcnt and pcnt < 498 and ypos_in_bands = '1' else '0';
  in_band6 <= '1' when 538 < pcnt and pcnt < 598 and ypos_in_bands = '1' else '0';
  
  in_band1_bar <= '1' when in_band1 = '1' and 9+380-38*amplitude1_bar < lcnt and lcnt < 4+9+380-38*amplitude1_bar else '0';
  in_band2_bar <= '1' when in_band2 = '1' and 9+380-38*amplitude2_bar < lcnt and lcnt < 4+9+380-38*amplitude2_bar else '0';
  in_band3_bar <= '1' when in_band3 = '1' and 9+380-38*amplitude3_bar < lcnt and lcnt < 4+9+380-38*amplitude3_bar else '0';
  in_band4_bar <= '1' when in_band4 = '1' and 9+380-38*amplitude4_bar < lcnt and lcnt < 4+9+380-38*amplitude4_bar else '0';
  in_band5_bar <= '1' when in_band5 = '1' and 9+380-38*amplitude5_bar < lcnt and lcnt < 4+9+380-38*amplitude5_bar else '0';
  in_band6_bar <= '1' when in_band6 = '1' and 9+380-38*amplitude6_bar < lcnt and lcnt < 4+9+380-38*amplitude6_bar else '0';
                                
  ypos_in_volume_and_blance <= '1' when 410 < lcnt and lcnt < 450 else '0';
  in_volume <= '1' when 38 < pcnt and pcnt < 298 and ypos_in_volume_and_blance = '1' else '0';
  in_balance <= '1' when 345 < pcnt and pcnt < 598 and ypos_in_volume_and_blance = '1' else '0'; --338
  in_volume_bar <= '1' when 38 < pcnt and pcnt < 38+26*volume and ypos_in_volume_and_blance = '1' else '0';
  in_balance_bar <= '1' when 345+balance*23 <pcnt and pcnt < 345 + (balance + 1)*23 and ypos_in_volume_and_blance = '1' else '0';
  
  process(fpga_clk)                
  begin
    
    
    if rising_edge(fpga_clk) and vga_clk ='1' then
      
    -- pos_amplitude := lcnt;
      
      -- x has to be decreas with 1 becaus of delay from true p_cnt counter value
    if 793 = pcnt or 638 = pcnt or 0 = lcnt or 479 = lcnt then -- Print frame
        vga_r <= (others=>'1');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0'); 
       
      elsif in_band1 = '1' then  -- Band 1
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band1_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude1 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
        
      elsif in_band2 = '1' then -- Band 2
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band2_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude2 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
      
      elsif in_band3 = '1' then -- Band 3
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band3_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude3 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
                 
      elsif in_band4 = '1' then -- Band 4
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band4_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude4 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
                
      elsif in_band5 = '1' then -- Band 5
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band5_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude5 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
        
      elsif in_band6 = '1' then -- Band 6
        vga_r <= (others=>'0');
        vga_b <= (others=>'0');
        vga_g <= (others=>'0');
        if in_band6_bar = '1' then
          vga_r <= (others=>'1');
        elsif l_cnt_to_amplitude <= amplitude6 then
        vga_g <= (others=>'1');
        else
          vga_g <= (others=>'0');
        end if;
          
      elsif in_volume = '1' then -- volume
          vga_b <= (others=>'0');
          vga_g <= (others=>'0');
        if in_volume_bar = '1' then
          vga_r <= (others=>'1');
        else
          vga_r <= (others=>'0');
      end if;
      elsif in_balance = '1' then -- balance
      vga_b <= (others=>'0');
      vga_g <= (others=>'0');
    if in_balance_bar = '1' then
      vga_r <= (others=>'1');
    else
      vga_r <= (others=>'0');
    end if;
      else
        vga_r <= (others=>'1');
        vga_g <= (others=>'1');
        vga_b <= (others=>'1');
      end if;
    end if;
    
  end process;
  
END ARCHITECTURE arch;

